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 STS17NF3LL
N-channel 30V - 0.0045 - 17A - SO-8 STripFETTM II Power MOSFET for DC-DC conversion
General features
Type STS17NF3LL

VDSS 30V
RDS(on) <0.0055
ID 17A
Optimal RDS(on) x Qg trade-off @ 4.5V Conduction losses reduced Switching losses reduced
SO-8
Description
This application specific Power MOSFET is the second generation of STMicroelectronis unique "Single Feature SizeTM" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. Such features make it the best choice in high efficiency DC-DC converters for Telecom and computer industries.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STS17NF3LL Marking S17NF3LL Package SO-8 Packaging Tape & reel
October 2006
Rev 5
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www.st.com 12
Contents
STS17NF3LL
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6
3 4 5
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STS17NF3LL
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VGS ID ID IDM
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Value 30 18 17 12 68 3.2 Unit V V A A A W
PTOT
1. Pulse width limited by safe operating area
Table 2.
Rthj-amb Rthj-lead Tj Tstg
Thermal data
Thermal resistance junction-ambient max (1) Thermal resistance junction-leads max Maximum operating junction temperature Storage temperature 47 16 -55 to 175 -55 to175 C/W C/W C C
1. When mounted on FR-4 board of 1in, 2oz Cu. t<10sec
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Electrical characteristics
STS17NF3LL
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 3.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250A, VGS =0 VDS = max rating VDS =max rating, TC = 125C VGS = 18V VDS = VGS, ID = 250A VGS = 10V, ID = 8.5A VGS = 4.5V, ID = 8.5A 1 0.0045 0.0055 0.0055 0.007 Min. 30 1 10 100 Typ. Max. Unit V A A nA V
IDSS
IGSS VGS(th) RDS(on)
Table 4.
Symbol gfs (1) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Total gate charge Gate-source charge Gate-drain charge Test conditions VDS = 10V, ID = 8.5A Min. Typ. 37 2160 614 98 23.5 39 47.5 37 26 7 12 35 Max. Unit S pF pF pF ns ns ns ns nC nC nC
VDS = 25V, f = 1MHz, VGS = 0
VDD = 15V, ID = 8.5A RG = 4.7 VGS = 4.5V (see Figure 13) VDD = 24V, ID = 12.5A, VGS = 4.5V, RG = 4.7 (see Figure 14)
1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
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STS17NF3LL
Electrical characteristics
Table 5.
Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 17A, VGS = 0 39 45 2.3 Test conditions Min. Typ. Max. 17 68 1.2 Unit A A V ns nC A
Reverse recovery time ISD = 17A, di/dt = 100A/s, Reverse recovery charge VDD = 15V; Tj = 150C Reverse recovery current (see Figure 15)
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %
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Electrical characteristics
STS17NF3LL
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
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STS17NF3LL Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
Figure 12. Normalized breakdown voltage vs temperature
7/12
Test circuit
STS17NF3LL
3
Test circuit
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
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STS17NF3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STS17NF3LL
SO-8 MECHANICAL DATA
DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019
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STS17NF3LL
Revision history
5
Revision history
Table 6.
Date 21-Jun-2004 04-Oct-2006
Revision history
Revision 4 5 Complete document New template, no content change Changes
11/12
STS17NF3LL
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